For more than half a century, Moore’s Law has served as the north star of semiconductor progress, predicting a doubling of transistor density roughly every two years. Though never a physical law, its prescience has driven unprecedented innovation and performance gains. But that trajectory is now under pressure. As engineers confront the physical and economic boundaries of miniaturization, Moore’s Law has shifted from a confident roadmap to an open question. At this year’s SPIE Lithography Conference, Erik Hosler, a consultant with deep expertise in EUV development and advanced patterning, highlighted patterning innovation as one of the few remaining levers capable of extending the law’s legacy into the next era.
This shift is not just about raw scaling. It is about engineering ingenuity and developing strategies, tools, and materials that allow features to continue shrinking while still achieving acceptable yield, performance, and cost. Advanced patterning sits at the center of that strategy, enabling structures that were once considered unprintable and pushing the boundaries of what optical lithography can accomplish.
Beyond the Limits of Classic Scaling
Several intertwined factors have driven the slowdown of traditional scaling, including quantum effects at atomic scales, rising fabrication costs at advanced nodes, and challenges in controlling variability across increasingly complex layers. While transistor sizes have shrunk into single-digit nanometers, each reduction now demands disproportionately more effort.
Advanced patterning techniques, particularly those using Extreme Ultraviolet (EUV) lithography, offer a partial solution. EUV, operating at a 13.5-nanometer wavelength, enables single-pattern exposures for features that previously required multiple passes and intricate overlay alignment. This simplification is vital not just for accuracy but also for manufacturing efficiency.
Yet the EUV itself is not a universal fix. At 5 nanometers and below, even EUV faces challenges with resolution, line edge roughness, and stochastic variation. That is where advanced patterning strategies such as pitch splitting, self-aligned patterning, and complementary techniques come into play.
What “Advanced Patterning” Really Means
Advanced patterning is not a singular technology. It is an evolving set of methods, tools, and philosophies aimed at stretching lithographic resolution beyond conventional limits. It includes optical proximity correction, spacer-based double and quadruple patterning, novel mask designs, and directed self-assembly.
Each of these techniques addresses different constraints. These include resolution, process variability, overlay error, and cost. The real innovation lies in how they are used together. In many layers, patterning strategies combine multiple exposures, new resist chemistries, and inline metrology feedback to optimize results.
Erik Hosler remarks, “We are looking at just about everything in advanced patterning.” It reflects the broadened search for progress. Engineers are no longer waiting for a single breakthrough. They are actively experimenting across disciplines, testing and refining what can deliver results on a scale.
The Role of EUV and High NA Systems
EUV lithography is now at the core of advanced patterning discussions. It reduces the number of process steps, lowers cumulative overlay errors, and enables tighter feature control. Chipmakers like TSMC and Samsung are using EUV in production nodes at 7 nanometers and beyond.
Attention is now shifting to High Numerical Aperture (High NA) EUV systems. These tools use modified optics to enable smaller printed features and better line fidelity. However, High NA systems also bring tighter focus margins, thinner resists, and heightened sensitivity to overlay error.
They do not eliminate the need for complementary techniques. In fact, their precision often exposes variations that previously went undetected. Successfully integrating high-NA systems will require further development in resist materials, etch chemistry, and process control tools.
Addressing Stochastic Variation
Among the most stubborn issues in advanced patterning are stochastic defects. These defects arise from quantum noise, resist inhomogeneity, or photon shot noise during exposure. Because they are not systematic, they are harder to model and mitigate.
To address this, engineers are adopting statistical simulation, higher exposure doses, and resists with more predictable performance under EUV radiation. At the same time, chip design itself is adapting. Circuits are being built with error tolerance in mind, using redundancy, error correction, or physical design rules that minimize risk zones.
Metrology is changing, too. Rather than measuring exact edge positions, tools now track variation profiles and process windows statistically, giving fabrications a better view of repeatability across wafers.
Integration and Co-Optimization
Advanced patterning is most effective when integrated across the manufacturing process. It must align with mask layout, etch strategy, resist selection, and metrology feedback. This integration is key because a gain in one area, say, resolution, can lead to problems in another, such as bias or line collapse.
For example, spacer-based patterning provides higher resolution but requires careful control of deposition thickness and etch selectivity. A new resist may reduce line roughness but require different bake temperatures and development times. Co-optimization ensures that these factors do not undermine yield or performance.
This complexity is why collaboration between foundries, toolmakers, and materials suppliers has become essential. No single company controls all the variables anymore. Progress now depends on ecosystem alignment.
Rethinking Design to Fit Patterning Limits
With patterning constraints growing tighter, chip designers are adjusting cell architectures to align with what lithography can reliably print. It includes reducing the number of routing tracks in logic cells, changing contact configurations, and shifting to unidirectional layouts.
These layout choices make it easier to achieve consistent critical dimensions and avoid hot spots. But they also require modern design tools, simulation models, and place-and-route algorithms that can work within those constraints without sacrificing performance.
Patterning constraints are now shaping the design process upstream. Rather than designing ideal circuits and adjusting during tape-out, teams begin with printability in mind.
A Multi-Path Future for Scaling
The future of semiconductor scaling is no longer linear. Transistor shrinking is just one path. Others include 3D integration, chiplet-based design, and heterogeneous stacking. In each of these areas, patterning plays a role.
For example, advanced die-to-wafer bonding requires sub-micron alignment and reliability via etching. Chiplets demand well-patterned interposers or bridges to route signals. As packaging and interconnect strategies grow more complex, so does the need for precise and scalable patterning.
Advanced patterning is not just about making features smaller. It is about making them work together across layers, substrates, and system levels.
Innovation Over Inertia
Moore’s Law may no longer follow a rigid two-year cadence, but its influence endures. Engineers continue to push for higher performance and lower power in smaller footprints. Advanced patterning is one of the key enablers of that effort, offering tools to extend scaling even as physics pushes back.
By expanding the patterning toolkit, embracing cross-disciplinary thinking, and designing with process limits in mind, the industry is finding ways to keep innovating. It is not a matter of defying limitations. It is a matter of engineering around them with creativity and discipline. As long as minds keep asking what else is possible and the industry remains willing to explore everything, Moore’s Law may keep breathing for a while longer.
